High speed divide-by-N circuit

Details High speed divide-by-N circuit High speed divide-by-N circuit

1975-10-02

1977-01-11

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307208, 307224C, 307279, 328 48, 235 92DM, H03K 2136

Patent

active

040029263

ABSTRACT:
Disclosed is a high speed divide-by-N circuit which uses both a synchronous down-counter and a ripple down-counter to obtain the advantages of each. The advantage of a ripple counter is that count propagation time is not critical, and the advantage of a synchronous counter is that its state can be decoded quickly. Therefore, by combining the two different types of counters, keeping the gate delays per clock cycle as low as possible, using look-ahead techniques, and giving more time-consuming operations more time to occur, a high speed divide-by-N circuit is obtained. Said circuit is intended for integration on a single chip, particularly using CMOS design and processing.

REFERENCES:
patent: 3614632 (1971-10-01), Leibowitz et al.
patent: 3646371 (1972-02-01), Flad
patent: 3706043 (1972-12-01), Reinert
patent: 3864582 (1975-02-01), Keeler
patent: 3899691 (1975-08-01), Hama
Arithmetic Operations In Digital Computers by R. K. Richards pp. 194-195, Sci. Lib. 1957.

Affiliated with

Also associated with

Rating

High speed divide-by-N circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High speed divide-by-N circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High speed divide-by-N circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1745499