Parallel path self-testing system

Details Parallel path self-testing system Parallel path self-testing system

1982-11-08

1985-03-05

Smith, Jerry

Excavating

324 73R, 364900, G06F 1100

Patent

active

045035377

ABSTRACT:
The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generators and also contain switching circuits to connect the scan paths of the chips in parallel between different stages of the random signal generator and the data compression means for random stimuli signature generators and to disconnect the scan paths from the signal generator and data compression circuitry and arrange them serially in a single scan path to perform other tests.

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