System and method for a multiple state, multiple case counter

Details System and method for a multiple state, multiple case counter System and method for a multiple state, multiple case counter

1997-03-06

1998-06-16

Ramirez, Ellis B.

G06F 1700

Patent

active

057685223

ABSTRACT:
A system and a method for a multiple state, multiple case counter circuit are disclosed. The counter circuit has a n position register, n being any integer. Each of the n position counts from 1 to 9. In one embodiment of the present invention, the register takes 9 states (state 1 to state 9). In another embodiment of the present invention, the register has 10 states (state 0 to state 9). Furthermore, the register takes n cases in each state. The counter circuit uses one of the n positions of the register to indicate a state of the register and uses the remaining (n-1) positions to count the NEs. The counter circuit counts 9.times.n.times.(1.sup.n-1 -1) NEs when the register has 9 states. Likewise, the counter circuit counts 10.times.n.times.(10.sup.n-1 -1) NEs when the register has 10 states.

REFERENCES:
patent: 5473596 (1995-12-01), Garafola et al.
patent: 5491796 (1996-02-01), Wanderer et al.
patent: 5528677 (1996-06-01), Butler et al.
patent: 5537547 (1996-07-01), Chan et al.
patent: 5544314 (1996-08-01), Fuchsreiter et al.
patent: 5687223 (1997-11-01), Elliott et al.

Affiliated with

Also associated with

Rating

System and method for a multiple state, multiple case counter does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with System and method for a multiple state, multiple case counter, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and System and method for a multiple state, multiple case counter will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1737496