Interleaved method and circuitry for testing for stuck open faul

Details Interleaved method and circuitry for testing for stuck open faul Interleaved method and circuitry for testing for stuck open faul

1987-07-30

1989-05-23

Excavating

371 25, G01R 3128

Patent

active

048336769

ABSTRACT:
A method and apparatus are disclosed for testing for stuck open faults in integrated circuits (10) having a plurality of combinational logic devices (18, 20). The apparatus includes a chain or shift register stages (22), with each stage including at lest two latches (L1and L2). Provision (43) is made for interleaving the bits of an initialization test pattern (40) with the bits of a detection test pattern (42) prior to loading the resultant serial data stream into the shift register stages (22). Once loaded, the latches (L2) contain the initialization test pattern whereas the latches (L1) hold the detection test pattern. A multiplexer (52) is provided for selecting one of the outputs from the two latches (L1, L2) so that the initialization test pattern and then the detection test pattern can be quickly applied to the combinational logic so as to minimize hazards which could invalidate the test results.

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patent: 4519078 (1985-05-01), Komonytsky
patent: 4553236 (1985-11-01), Zasio et al.
patent: 4621363 (1986-11-01), Blum
patent: 4697279 (1987-09-01), Baratti et al.
patent: 4698588 (1987-10-01), Hwang et al.
Craig et al., "Pseudo-Exhaustive Adjacency Testing: a Bist Approach for Stuck-Open Faults", 1985 International Test Conference, pp. 126-137, 1985.
Eichelberger et al., "A Logic Design Structure for LSI Testability", Proc. 14th Design Automation Conference, New Orleans, Jun. 20-22, 1977.

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