Excavating
Patent
1996-03-28
1998-06-16
Nguyen, Hoa T.
Excavating
371 225, G01R 3128
Patent
active
057682887
ABSTRACT:
A programmable logic device having a plurality of programmable elements includes a fast verify method and test circuit for programming the programmable logic device. The test circuit includes a serial input port and an address storage element which receives address information from the serial input port. The test circuit also incudes a data storage element which receives program data from the serial input port. The test circuit additionally includes control logic coupled to the address storage element and the data storage element. The control logic controls when the program data is provided to a memory location and read from a memory location as verify data. The test circuit further includes verify logic coupled to the data storage element and the memory location. The verify logic generates an output signal in response to a comparison of the verify data and the program data. The verify logic uses the program data as a mask in generating the output signal. The output signal may indicate a match between the program data and the verify data. The verify logic may comprise a verify register coupled to compare logic. The verify logic may generate a comparison result in response to a transition of a clock signal.
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Cypress Semiconductor Corp.
Nguyen Hoa T.
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