Circuit for evaluating bit error rate performance of a data deco

Details Circuit for evaluating bit error rate performance of a data deco Circuit for evaluating bit error rate performance of a data deco

1996-05-31

1998-06-16

Beausoliel, Jr., Robert W.

Excavating

371 28, 371 43, 375262, 375341, G06F 1100

Patent

active

057682852

ABSTRACT:
An evaluation circuit for use in evaluating the bit error rate (BER) performance of a Viterbi detector based upon a computation of its amplitude error margin (AEM) includes two threshold comparison circuits and an AEM computation circuit. Each threshold comparison circuit receives and compares a Viterbi signal from a Viterbi detector and one or two AEM threshold signals and in accordance therewith generates a comparison signal. The Viterbi signals represent combinations of signals which include the sum of and difference between the Viterbi difference metric and slicer threshold signals associated with the Viterbi detector. The AEM threshold signals correspond to probabilities that the two Viterbi signals have magnitudes which exceed some predetermined values. The AEM computation circuit receives a control signal from the Viterbi detector and the two comparison signals and computes an AEM parameter which corresponds to one of the Viterbi signals. In one embodiment: each threshold comparison circuit includes a converter which converts the Viterbi signal to an absolute value signal representing the absolute value of the Viterbi signal, a comparator which compares the absolute value signal with an AEM threshold signal, and a shift register which receives and time-delays the comparator output signal to generate the comparison signal; and the AEM computation circuit includes a multiplexor which selects between the comparison signals in accordance with the control signal, and a counter which counts the signal transitions of the selected comparison signal. The counter output represents the AEM of the Viterbi detector.

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