MOS FET semiconductor device having a cell pattern arrangement f

Details MOS FET semiconductor device having a cell pattern arrangement f MOS FET semiconductor device having a cell pattern arrangement f

1988-09-27

1989-05-23

Carroll, J.

357 238, 357 41, 357 65, 357 68, H01L 2978, H01L 2702, H01L 2348

Patent

active

048335134

ABSTRACT:
A semiconductor device, i.e. diffusion-self-alignment MOS FET including an n type first semiconductor layer, a p type second semiconductor layer formed in a surface of the first semiconductor layer, an n.sup.+ type third semiconductor layer formed in the second semiconductor layer, a poly-silicon film pattern formed on the first semiconductor layer via a first insulating film, a second insulating film formed on the polysilicon film, and a metal electrode film formed on the second insulating film. A unit pattern of the second and third semiconductor layers and poly-silicon film have two or three enlarged portions and thin elongated portions connecting the enlarged portions to each other, and the metal electrode film is connected to the second and third semconductor layers through openings formed in the second insulating film within the enlarged portions. A number of unit patterns are arranged interdigitally.

REFERENCES:
patent: 4677452 (1987-06-01), Zommer
F. Mohammadi, "Silicide for Interconnection Technology," Solid State Technology, (Jan. 1981), pp. 65-72.

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