Multi I/O device system using temporary store of RAM data when a

Details Multi I/O device system using temporary store of RAM data when a Multi I/O device system using temporary store of RAM data when a

1990-10-30

1993-08-10

Dixon, Joseph L.

Boots, shoes, and leggings

395275, 395375, 395550, 364DIG1, 3642384, 3642423, 36424231, 3642494, G06F 1200

Patent

active

052356949

ABSTRACT:
When a data read timing of a DMAC is not matched with an output timing of data read out from a DRAM, the readout data is held in a register until a subsequent data read timing of the DMAC comes to the front. When data is read out from the DRAM, and if a processor clock of the DMAC has a phase matched with that of an operation clock of the DRAM, then a direct read operation is performed. If the phases of the two clocks are not matched with each other, the readout data from the DRAM is temporarily stored in the register and then fetched in the DMAC.

REFERENCES:
patent: 4545014 (1985-10-01), Oguchi
patent: 4792929 (1988-12-01), Olson et al.
patent: 4912632 (1990-02-01), Gach et al.

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