Test circuit and test method of integrated semiconductor device

Details Test circuit and test method of integrated semiconductor device Test circuit and test method of integrated semiconductor device

1995-02-08

1997-05-20

Beausoliel, Jr., Robert W.

Excavating

371 225, 371 223, G06F 1100

Patent

active

056319134

ABSTRACT:
In a test circuit of an integrated semiconductor device such as a memory, a parallel-input linear feedback shift register (LFSR) is used for both compressing data and comparing the obtained compressed value with an expected compressed value, thereby judging whether or not the integrated semiconductor device under test is normal. The parallel-input LFSR comprises a plurality of registers, a plurality of 2-input exclusive-OR gates placed in the stages previous to the respective registers mentioned above, and a feedback information generating means for generating feedback information from the output from the final-stage register and from the output from the register in a specified middle stage. In testing the integrated semiconductor device, the parallel-input LFSR compresses sequential sets of data from the integrated semiconductor device so as to obtain a compressed signature and then supplies the first input of the 2-input exclusive-OR gate placed in the leftmost position with the output from the final-stage register, while supplying the first inputs of the other exclusive-OR gates with the outputs from the registers in their respective previous stages. The second input of each of the exclusive-OR gates is supplied with an expected signature. Thus, the compressed value is compared with the expected compressed value at the respective exclusive-OR gates of the parallel-input LFSR.

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