System decoder circuit and method of operation

Details System decoder circuit and method of operation System decoder circuit and method of operation

1995-06-07

1997-05-20

Ramirez, Ellis B.

Boots, shoes, and leggings

G06F 1900

Patent

active

056318480

ABSTRACT:
A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

REFERENCES:
patent: 3691553 (1972-09-01), McIntosh
patent: 4217660 (1980-08-01), En
patent: 5425061 (1995-06-01), Laczko, Sr. et al.
patent: 5432512 (1995-07-01), Park
patent: 5473566 (1995-12-01), Rao

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