Dynamic random access memory cell having a stacked-trench capaci

Details Dynamic random access memory cell having a stacked-trench capaci Dynamic random access memory cell having a stacked-trench capaci

1992-04-15

1993-08-10

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 52, 437203, 437919, H01L 2144, H01L 2170

Patent

active

052348563

ABSTRACT:
A new stacked-trench DRAM cell has a trench that is self-aligned to an adjacent field oxide region and the dielectric spacer insulated edge of the access transistor gate. The trench is lined with dielectric material and an arsenic-doped polysilicon storage node plate makes contact with the storage node junction on a horizontal surface on the lip of the trench. The horizontal surface is exposed following trench formation by etching away an outer portion of the transistor gate spacer, which is comprised of a material that is selectively etchable with respect to an inner portion of the spacer. Since the contact area between the storage node plate and the storage node junction is limited to this very small area, the potential for leakage of capacitor charge into the substrate is minimized.

REFERENCES:
patent: 4951175 (1990-08-01), Kurusawa et al.
patent: 4975383 (1990-12-01), Baglee
patent: 5066608 (1991-11-01), Kim et al.

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