Method of fabricating a nitride capped MOSFET for integrated cir

Details Method of fabricating a nitride capped MOSFET for integrated cir Method of fabricating a nitride capped MOSFET for integrated cir

1990-09-04

1993-08-10

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 30, 437 34, 437 41, 437 57, 257338, 257344, 257369, H01L 21336, H01L 27092

Patent

active

052348504

ABSTRACT:
A method is described for fabricating a lightly doped drain MOSFET integrated circuit device. The method begins by forming a pattern of gate electrode structures upon a semiconductor substrate which structures each includes a gate oxide, a polysilicon layer and a refractory metal silicide. A thin silicon nitride layer is formed over each of the structures and the exposed surfaces therebetween of the substrate. A pattern of lightly doped regions in the substrate is formed by ion implantation using the polycide gate structures as the mask. A dielectric spacer structure is formed upon the sidewalls of each of the polycide gate structures and over the adjacent portions of the substrate. A pattern of heavily doped regions in the substrate is formed by ion implantation using the polycide structures with spacer structures as the mask to produce the lightly doped drain source/drain structures of an MOSFET device. The integrated circuit device is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover to electrically connect the gate electrode structures and source/drain elements.

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