System for bumpless changeover between active units and backup u

Details System for bumpless changeover between active units and backup u System for bumpless changeover between active units and backup u

1987-09-18

1990-07-10

Eng, David Y.

Boots, shoes, and leggings

364268, 3642683, 3642692, 3642671, 364187, 371 12, G06F 1120, G06F 1130

Patent

active

049410873

ABSTRACT:
The central unit of a computer equipment has a processor and a memory as well as redundant units as backup units for the processor and/or the memory. Further, there are members for changeover from an active unit to a corresponding backup unit in the event of a fault in the active unit. The central unit has interrupt routines and carries out write and read operations against the peripheral units of the equipment. A bumpless changeover from an active unit to a backup unit is obtained by establishing rollback points (P.sub.0 -P.sub.4) in the program execution by storing the processor state and the memory content in at least all hardware initiated interrupt routines; by logging all operations against the peripheral units after each rollback point; by returning the program execution, after a changeover (at P.sub.f) to a backup unit, to the last established rollback point (P.sub.1); and by thereafter resuming the execution without performing any operations against the peripheral units, whereby instead the result of read operations is fetched from the log and write operations are skipped, until all the logged operations have been repeated; and by thereafter continuing the execution while performing operations against the peripheral units.

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