Self-diagnostic system for semiconductor memory

Details Self-diagnostic system for semiconductor memory Self-diagnostic system for semiconductor memory

1991-10-28

1993-12-14

Beausoliel, Jr., Robert W.

Excavating

371 251, G11C 2900

Patent

active

052710157

ABSTRACT:
A self-diagnostic memory checking system includes a data generator for generating and applying data to a selected address of a memory when a CPU is in a memory write mode and generating expected data when the CPU is in a memory read mode. An address generator provides a memory address for the memory. The data is read out of the memory during the memory read mode and is compared to the expected data for detecting errors in the memory. In order to allow memory checking to proceed without constant action by software in the CPU, a range of memory addresses to be tested are loaded into a test finish detector. A separate clock generator provides enabling timing clock pulses to the address generator, data generator and memory in response to a test start signal from the CPU. A switch circuit connects data from the data generator to a first output connected to the data input of the memory when the CPU is in the memory write mode and to a second output when the CPU is the memory read mode. A comparator connected to the output of the memory for comparing the data read from the memory and to the expected data from the second output of the switch circuit gives an output representative of whether the expected data and the data read from the memory are in coincidence. A flip-flop receives the output of the comparator and indicates the result of the comparison.

REFERENCES:
patent: 4423508 (1983-12-01), Shiozaki et al.
patent: 4916696 (1990-04-01), Funakubo
patent: 4972418 (1990-11-01), Chou
patent: 5012423 (1991-04-01), Bailey et al.

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