Peripheral processor multifunction timer for data processing sys

Details Peripheral processor multifunction timer for data processing sys Peripheral processor multifunction timer for data processing sys

1978-09-25

1980-09-02

Malzahn, David H.

Boots, shoes, and leggings

G06F 918

Patent

active

042209900

ABSTRACT:
A peripheral processor (13) and associated memory (21) cooperate with a main processor (10) in a data processing system to provide for the main processor multiple parallel timing channels (7) for timing functions of various durations in an extensive range of duration magnitudes. The main processor initiates the timing of an event by interrupting the peripheral processor to specify a device and the duration of its function to be timed for each such function as the need for each timing operation arises. The peripheral processor administers all of the timing channels are queues (8) time-outs as they occur and pending notification of the main processor of the time-out by an interrupt request. Such interrupt requests are generated in a predetermined order with respect to factors such as the order of occurrence of the time-out and the relative interrupt priority of the timed function.

REFERENCES:
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patent: 3947824 (1976-03-01), Doehle et al.
patent: 4016541 (1977-04-01), Delagi et al.
patent: 4090239 (1978-05-01), Twibell et al.
patent: 4099232 (1978-07-01), Mensch, Jr.
Haur et al., "Organization of the No. 1 ESS Stored Program", Bell System Technical Journal, Sep. 1964, pp. 1870-1872, 1927-1929 & 1950-1952.

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