Semiconductor memory device having a memory cell capacitor and a

Details Semiconductor memory device having a memory cell capacitor and a Semiconductor memory device having a memory cell capacitor and a

1994-08-29

1995-05-09

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, 356357, 34082595, 437 52, H01L 27108

Patent

active

054146364

ABSTRACT:
A method for fabricating a dynamic random access memory comprises the steps of determining a design rule for word lines and bit lines and further for a pattern that extends from a memory cell array region to a peripheral region across a stepped boundary, determining a step height of the stepped boundary based upon the design rule, determining a capacitance of the memory cell capacitor based upon the step height of the stepped boundary, determining a parasitic capacitance of a bit line such that a ratio of the parasitic capacitance to the capacitance of the memory cell is smaller than a predetermined factor, and determining the number of the memory cells that are connected to one bit line based upon the parasitic capacitance of the bit line.

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Fujio Masuoka, Toshiba Corp.; Are You Ready for Next-Generation Dynamic Ram Chips?; Nov. 27, 1990; vol. 27, No. 11, pp. 110-112; New York, US.

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