Electricity: electrical systems and devices – Safety and protection of systems and devices – Transient responsive
Patent
1995-12-05
1998-11-24
Gaffin, Jeffrey A
Electricity: electrical systems and devices
Safety and protection of systems and devices
Transient responsive
361 56, 361118, 361119, H02H 300
Patent
active
058416196
ABSTRACT:
To an input terminal is connected one end of the source-to-drain current path of an NMOS the gate of which is connected to Vcc. The other end of the current path of the NMOS is connected by a protection circuit comprised of a PMOS and an NMOS to the common gates of a PMOS and an NMOS in the input stage of an internal circuit. In the protection circuit, the PMOS has its source and gate connected to Vcc and its drain connected to the common gates of the PMOS and the NMOS, while the NMOS has its source and gate connected to Vss and its drain connected to the common drains of the PMOS and the NMOS.
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patent: 5430595 (1995-07-01), Wagner et al.
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patent: 5455436 (1995-10-01), Cheng
Wong, D. T. et al., IEEE J. Solid-State Circuits, "An 11-ns 8K X 18 CMOS Static RAM with 0.5-um Device ", vol. 23, No. 5, pp. 1095-1103, dated Oct. 5, 1988.
Ueda, M. et al; IEEE 1993 CICC, 25.5.1, "3.3V ASIC for Mixed Voltage Applications with Shut Down Mode".
Masumi Junya
Shigehara Hiroshi
Tanaka Yasunori
Gaffin Jeffrey A
Jackson Stephen
Kabushiki Kaisha Toshiba
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