Phase locked loop including non-integer multiple frequency refer

Details Phase locked loop including non-integer multiple frequency refer Phase locked loop including non-integer multiple frequency refer

1990-08-14

1991-09-24

Safourek, Benedict V.

Pulse or digital communications

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328 16, 328 55, 331 1A, 331 25, H03L 706

Patent

active

050520318

ABSTRACT:
A digital phase locked loop is employed to realize an output clock signal from a reference signal having a frequency which is not an integer multiple of the output clock signal frequency. This is realized by employing a programmable divider for dividing the reference signal which is dynamically controlled by a controllably variable base divisor. The base divisor control is responsive to the reference signal and to a phase error signal. The base divisor is generated to obtain a desired fractional division of the reference signal frequency and in a manner to minimize the amplitude of any resulting "high" frequency jitter in the output clock signal from the loop.

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patent: 4903283 (1990-02-01), Eisenberg
Digital PLL Frequency Synthesizers, Theory and Design, Ulrich L. Rohde, Ph.D., Sc.D., 1983 Prentice-Hall, Inc., pp. 124-125.
High Speed CMOS Data Manual, Signetics, .COPYRGT.1988, pp. 7-444-7.446, 7-448-7-451, 7-983-7-985.

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