Boots – shoes – and leggings
Patent
1989-06-23
1991-09-24
Dixon, Joseph L.
Boots, shoes, and leggings
364900, 3649163, 364580, 364488, 371 23, G06G 748, G06F 1100
Patent
active
050519387
ABSTRACT:
A system and method for selectively simulating logic circuit designs in which a data tables generator receives information from a schematic entry program or netlist entry file and produces data tables for use by a simulator. A designer provides inputs to the data tables generator from a schematic entry program or a netlist entry file. The data tables generator generates from the information received a table of used integrated circuits and a table of their connections. A simulator then receives the output from the data tables generator and produces a design simulation program table that executes integrated circuit model subroutine stored in an integrated circuit model reference library and netlist subroutines stored in a netlist connectivity table. The system may also be used for testing logic circuits on a printed circuit board by capturing signals from a potentially defective logic section of the printed circuit board and feeding them into test points of the integrated circuit simulated by the computer simulator.
REFERENCES:
patent: 3961250 (1976-06-01), Snethen
patent: 4587625 (1986-05-01), Marino, Jr. et al.
patent: 4744084 (1988-05-01), Beck et al.
patent: 4782440 (1988-11-01), Nomizu et al.
patent: 4791593 (1988-12-01), Hennion
patent: 4802165 (1989-01-01), Ream
patent: 4817093 (1989-03-01), Jacobs et al.
patent: 4827427 (1989-05-01), Hyduke
patent: 4882690 (1989-11-01), Shinsha et al.
patent: 4891773 (1990-01-01), Ooe et al.
patent: 4896272 (1990-01-01), Kurosawa
patent: 4939681 (1990-07-01), Yokomizo et al.
patent: 4967386 (1990-10-01), Maeda et al.
Darringer, J. A., "A New Look at Logic Synthesis", 17th D.A. Conference 1980, pp. 543-549.
Nash et al., "A Front End Graphic Interface to the First Silicon Complier" European Conference on Electronic Design Automation, 26-30 Mar. 1984, pp. 120-125.
de Geus et al., "A Rule-Based System for Optimizing Combinational Logic", IEEE Design and Test, Aug. 1985, pp. 22-32.
Dixon Joseph L.
O'Reilly David
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