Boots – shoes – and leggings
Patent
1989-12-28
1991-12-03
Fleming, Michael R.
Boots, shoes, and leggings
3642412, 3642414, 3642415, 3642416, 3649410, 3649413, 3649416, 3649417, 364DIG1, 364DIG2, G06F 946
Patent
active
050704478
ABSTRACT:
An interrupt circuit for a microcomputer, in which requests for multiple interrupt processing arise at the same time, are executed in the assigned priority order. To assign a processing priority, the interrupt circuit comprises a first priority assignment control circuit and a second priority assignment control circuit. Furthermore, in order to execute a high priority interrupt processing with a minimum lag time, the present invention comprises the steps of: issuing a software interrupt request signal assigned a lower priority while executing an interrupt request based on a request signal assigned a high priority level; executing a minimum required processing based on the request signal with a high priority level; executing and completing processing based on a request signal assign a low priority level; and resuming, by the software interrupt request signal, a rest part of the interrupted processing based on the request signal with a high priority level, whereby the plurality of interrupt requests which occurred at the same time can be processed with high efficiency
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Economidis, "A Microprogrammable, Bipolar, LSI Interrupt Structure Using the AM2914", Am2914 Priority Interrupt Encoder, 1976, 1-21.
Fleming Michael R.
Hauser Robert S.
Sanyo Electric Co,. Ltd.
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