Prevention of parasitic mechanisms in junction isolated devices

Details Prevention of parasitic mechanisms in junction isolated devices Prevention of parasitic mechanisms in junction isolated devices

1989-02-10

1991-09-24

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 47, 307303, H03K 301, H03K 326

Patent

active

050516124

ABSTRACT:
A method of preventing forward biasing of PN junctions in junction isolated semiconductor devices to prevent parasitic transistor action. A biasing element is connected to the substrate/isolation regions to switch the regions to a low potential. The method is particularly well suited for implementation in the new multi-epitaxial semiconductor processes and structures.

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patent: 4633095 (1986-12-01), Komatu
patent: 4704705 (1987-11-01), Womack
patent: 4888623 (1989-12-01), Enomoto et al.
"Isolation Method and Structure for Integrated Devices", IBM Technical Disclosure Bulletin, by Pieczonka et al., vol. 8, No. 4, Sep. 1965.

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