Method of making dense flash EEprom semiconductor memory structu

Details Method of making dense flash EEprom semiconductor memory structu Method of making dense flash EEprom semiconductor memory structu

1989-03-15

1991-12-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437 52, 437233, H01L 21265

Patent

active

050700324

ABSTRACT:
An improved electrically erasable and programmable read only memory (EEprom) structure and processes of making it which results in a denser integrated circuit, improved operation and extended lifetime. In order to eliminate certain ill effects resulting from tolerances which must be allowed for registration of masks used in successive steps in forming the semiconductor structures, spacers are formed with reference to the position of existing elements in order to form floating gates and define small areas of these gates where, in a controlled fashion, a tunnel erase dielectric is formed. Alternatively, a polysilicon strip conductor is separated into separate control gates by a series of etching steps that includes an anisotropic etch of boundary oxide layers to define the area of the control gates that are coupled to the erase gate through an erase dielectric. In either case, the polysilicon layer strip can alternatively be separated by growing oxide thereon until it is completely consumed. A technique for forming a pure oxide dielectric layer of uniform thickness includes depositing a thin layer of an undoped polysilicon material and then oxidizing its surface until substantially the entire undoped polysilicon layer is consumed and made part of the resulting oxide layer. Overlapping doped regions are provided in the substrate by an ion implantation mask that adds spacers to the mask aperture to change its size between implants.

REFERENCES:
patent: 4239559 (1980-12-01), Ito
patent: 4804637 (1989-02-01), Smayling et al.
patent: 4814286 (1989-03-01), Tam
patent: 4852062 (1989-07-01), Baker et al.
patent: 4853895 (1989-08-01), Mitchell et al.
Mizutani and Makita, "A New EPROM Cell with a Side-wall Floating Gate for High-Density and High-Performance Device", IDEM 85, pp. 635-639, 1985.

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