Semiconductor memory device having multi-gate transistors

Details Semiconductor memory device having multi-gate transistors Semiconductor memory device having multi-gate transistors

1978-04-10

1980-11-11

Munson, Gene M.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

357 23, 357 41, 357 48, 357 54, 365184, H03K 500, H01L 2978, H01L 2702, G11C 1134

Patent

active

042335264

ABSTRACT:
A semiconductor memory device which may be formed in a parallel array for high density integration is disclosed. The memory device includes a multigate memory transistor formed in a first semiconductor region of one conductivity type in a substrate of the opposite conductivity type. The memory transistor is formed with source and drain regions of opposite conductivity type and a gate insulating layer formed on the surface between the source and drain regions. A plurality of gate electrodes are formed on the gate insulating layer and laterally separated from each other. A plurality of opposite conductivity type regions are formed in the first semiconductor region under the respective intervals between adjacent gate electrodes.

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Yamaguchi et al., "Circuit Array and System of MAOS Type Fully Decoded Electrically Alterable Read Only Memory-IC", Japanese Journal Applied Physics, vol. 13 (9/74) pp. 1414-1420.

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