Clock recovery enhancement circuit

Details Clock recovery enhancement circuit Clock recovery enhancement circuit

1991-03-22

1992-07-28

Chin, Stephen

Pulse or digital communications

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307269, 328 63, H03D 324

Patent

active

051346370

ABSTRACT:
An improved clock recovery enchancement circuit is provided that is particularly adapted for solving the problem caused by an incoming signal that is asymmetric and comprises a sub-harmonic tone of the bit rate clock, that is 180.degree. out of phase with the recovering clock, thereby causing the data edges to appear to be locked. The clock recovery enhancement circuit, according to the invention, provides a window signal near a predefined edge of the recovering clock which creates a disable signal such that clock adjustments may be biased towards one direction.

REFERENCES:
patent: 4280099 (1981-07-01), Rattlingourd et al.
patent: 4357707 (1982-11-01), Delury
patent: 4841167 (1989-06-01), Saegusa

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