Patent
1991-03-29
1992-07-28
Mintel, William
357 233, 357 238, 357 41, 357 54, 357 52, H01L 2978
Patent
active
051344521
ABSTRACT:
The MIS transistor according to the present invention includes insulating layers formed by the CVD method as gate insulating layers. The gate insulating layers formed by the CVD method have a uniform film thickness on the channel region surface roughened by etching treatment or the like. Thus, dielectric breakdown strength of the gate insulating layer is assured.
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Huang et al., "A MOS Transistor with Self-Aligned Polysilcon Source-Drain", IEEE Electron Device Letters, vol. 7, No. 5, May 1986, pp. 314-316.
Shimizu Masahiro
Yamaguchi Takehisa
Loke Steven
Mintel William
Mitsubishi Denki & Kabushiki Kaisha
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