MIS type FET semiconductor device with gate insulating layer hav

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357 233, 357 238, 357 41, 357 54, 357 52, H01L 2978

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active

051344521

ABSTRACT:
The MIS transistor according to the present invention includes insulating layers formed by the CVD method as gate insulating layers. The gate insulating layers formed by the CVD method have a uniform film thickness on the channel region surface roughened by etching treatment or the like. Thus, dielectric breakdown strength of the gate insulating layer is assured.

REFERENCES:
patent: 3899373 (1975-08-01), Antipov
patent: 4758530 (1988-07-01), Schubet
patent: 4791074 (1988-12-01), Tsunashima et al.
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4855247 (1989-08-01), Ma et al.
patent: 4954867 (1990-09-01), Hosaka
patent: 5021851 (1991-06-01), Haken et al.
Huang et al., "A MOS Transistor with Self-Aligned Polysilcon Source-Drain", IEEE Electron Device Letters, vol. 7, No. 5, May 1986, pp. 314-316.

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