Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-10-28
1999-06-08
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, 438692, 148DIG50, H01L 2176
Patent
active
059111100
ABSTRACT:
A thin silicon dioxide layer and a silicon nitride layer are respectively formed on a wafer. A plurality of shallow trenches are formed in the wafer. A trench filling layer is successively refilled into the trenches for isolation. A reverse tone mask with a dummy pattern mask is patterned on top of the trench filling material. An etching is performed to etch the trench filling material using the reverse tone mask and the dummy pattern mask as etching masks. The reverse tone mask and the dummy pattern mask are then stripped away. A chemical mechanical polishing (CMP) technology is used to remove the trench filling layer to the surface of the silicon nitride layer for planarization.
REFERENCES:
patent: 5459096 (1995-10-01), Venkatesan et al.
patent: 5578519 (1996-11-01), Cho
patent: 5811345 (1998-09-01), Yu et al.
Dang Trung
Taiwan Semiconductor Manufacturing Co. Ltd.
LandOfFree
Method of forming shallow trench isolation with dummy pattern in does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of forming shallow trench isolation with dummy pattern in, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of forming shallow trench isolation with dummy pattern in will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1688660