Patent
1997-02-25
1999-06-08
Coleman, Eric
39580032, 39580034, 39580036, G06F 1500
Patent
active
059110821
ABSTRACT:
A parallel processing building block (PPBB) chip comprises a low performance programmable digital signal processor (DSP) to implement relatively low intensity processing functions and includes a bus control for address and data communication. A medium performance programmable DSP to implement relatively medium intensity processing functions and includes a bus control for address and data communication. A high performance programmable DSP to implement relatively high intensity processing functions and includes a bus control for address and data communication. A serial and parallel bus controller provides external connectivity to a host system bus. A data router controller is connected to the bus control of each of the high, medium and low DSP's, and to the bus controller, and includes a memory interface controller for connection to an external RAM system, and a data router for controlling data movement between any of the high, medium and low DSP's, the memory interface controller, the bus controller as well as to other PPBB chips.
REFERENCES:
patent: 4862407 (1989-08-01), Fette et al.
patent: 5155852 (1992-10-01), Murakami et al.
patent: 5442789 (1995-08-01), Baker et al.
patent: 5590345 (1996-12-01), Barker et al.
"Two, Two Chips in One|", Tom Thompson, Byte Magazine, Jun. 1996.
Messer Dion Dee
Monroe Midori Jean
Audio DigitalImaging Inc.
Coleman Eric
Monestime Mackly
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