Apparatus for bypassing intermediate results from a pipelined fl

Details Apparatus for bypassing intermediate results from a pipelined fl Apparatus for bypassing intermediate results from a pipelined fl

1997-03-31

1999-11-30

Ellis, Richard L.

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

G06F 938

Patent

active

059960655

ABSTRACT:
A microprocessor having a pipelined floating point unit operable to bypass pre-rounded results at clock cycle i and provide the pre-rounded results as an operand for a second instruction at clock cycle i+2. In one embodiment, the pipelined execution unit includes at least a first execution step at clock cycle i, and a second execution step at a clock cycle i+1 and clock cycle i+2. The unit includes a bypass leading from the first execution step at clock cycle i, however, there is no bypass leading from the second execution step at clock cycle i+1. The bypass carries the pre-rounded results from the end of the first execution step to the front end of the pipeline via a latched data path which delays the pre-rounded result one clock cycle.

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patent: 5638526 (1997-06-01), Nakada
patent: 5805852 (1998-09-01), Nakanishi

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