Electrical computers and digital processing systems: processing – Processing architecture
Patent
1997-06-24
1999-11-30
An, Meng-Ai T.
Electrical computers and digital processing systems: processing
Processing architecture
712 23, 712 32, 712221, 708490, 708495, 708498, 708519, 710104, 710107, 710126, 710128, 710129, 710130, G06F 1516
Patent
active
059960566
ABSTRACT:
An intermediate result signal arising from a manipulation of data signals is checked and reduced without using conditional branches, thereby improving instruction processing. Data signals are represented as signed 8-bit binary values in a two's compliment format. This requires that the intermediate result signal be stored in a register that is greater than 8-bits wide to allow for the proper checking of an overflow condition. A processor operating under program control with the program has the following operations. The program determines whether the intermediate result signal is in a positive overflow state or a negative overflow state. A first mask signal is set to have 8 lower bits in an OFF position when the intermediate result signal is inside the range of a signed 8 bit integer. Otherwise, the first mask signal is set to have 8 lower bits in an ON position. Also, a second mask signal is set to have 8 lower bits in the OFF position when the intermediate result signal is not in the positive or negative overflow state. Otherwise, the second mask signal is set to an upper threshold signal when the data signal is in an overflow state or setting the second mask signal to a lower threshold signal when the data signal is in a negative overflow state. The intermediate result is bitwise ANDed with the first mask signal to obtain a translated data signal, and the translated data signal is bitwise ORed with the second mask signal.
REFERENCES:
patent: 4675725 (1987-06-01), Parkyn
patent: 4945507 (1990-07-01), Ishida et al.
patent: 5222159 (1993-06-01), Kawamura et al.
patent: 5402368 (1995-03-01), Yamada et al.
patent: 5402506 (1995-03-01), Schafer
patent: 5408670 (1995-04-01), Davies
patent: 5508951 (1996-04-01), Ishikawa
patent: 5539685 (1996-07-01), Otaguro
patent: 5734744 (1998-03-01), Wittenstein et al.
patent: 5887181 (1999-03-01), Volkonsky
patent: 5896396 (1999-04-01), Sanghani et al.
"The UltraSPARC Processor--Technology White Paper; The UltraSPARC Architecture," pp. 1-10, Copyright 1994-1997 Sun Microsystems, Inc., Palo Alto, CA.
An Meng-Ai T.
Nguyen Dzung
Sun Microsystems Inc.
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