Parallel computer with distributed shared memories and distribut

Details Parallel computer with distributed shared memories and distribut Parallel computer with distributed shared memories and distribut

1987-08-14

1990-08-21

Shaw, Gareth D.

Boots, shoes, and leggings

3642281, 3642303, 3642813, G06R 900

Patent

active

049511939

ABSTRACT:
In accessing a memory, each element processor executes a program constructed so as to designate an address belonging to a predetermined local address area for each element processor. When a memory write instruction is executed by an element processor, it is detected if the memory address designated by the instruction coincides with a predetermined address. If detected, a predetermined address belonging to a local address space of another element processor and assigned to the first-mentioned predetermined address, and the data written in response to the write instruction, are sent to the other element processor to instruct the data to be written therein as a copy data. A next task to be executed is decided independently for each element processor.

REFERENCES:
"The IBM Research Parallel Processor Prototype (RP3) Introduction and Architecture", Proc. of the 1985 ICPP (1985), by G. F. Pfister et al.
"Cedar, COMPCON '84 Spring", D. D. Gajski et al., pp. 306-309, 1984.
"The Piecewise Data Flow Architecture: Architectural Concepts", Joseph E. Requa, IEEE Transactions on Computers, vol. C-32, No. 5, May 1983.
"High-Speed Method in Computer for Technological Computation", Nikkei Electronics, Aug. 3, 1981; pp. 131-132.
"OCCAM Programming Manual", 3.3.2, 3.3.3, 3.5.2, and 3.12.4.

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