Isolation of insulated-gate field-effect transistors

Details Isolation of insulated-gate field-effect transistors Isolation of insulated-gate field-effect transistors

1988-08-19

1990-08-21

Hille, Rolf

357 234, 357 42, H01L 2712

Patent

active

049511173

ABSTRACT:
A semiconductor device and a method of fabricating the same wherein a semiconductor substrate of one conductivity type is formed of three laterally arrayed portions by providing two trenches in the substrate and filling them with first and second epitaxial layers of an opposite conductivity type. A buried layer of the opposite conductivity type is formed within the substrate. First and second insulator films are provided on the side walls of both trenches. The first portion of the substrate has a first region of one conductivity type. A second region of the one conductivity type is buried within the substrate. A third region of the opposite conductivity type is interposed in the direction of substrate depth between the first and second insulator films. The portion of the substrate includes a fourth region isolated from the first to third regions by the first insulator film. The third portion of the substrate includes a fifth region of the one conductivity type electrically connected to the second region. The first, second and fourth region work as one and the other of drain and source regions, and the gate of a vertical MOS transistor, respectively, and the fifth region is used for electrical connection to the buried second region.

REFERENCES:
patent: 4570330 (1986-02-01), Cogan
patent: 4661202 (1987-04-01), Ochii
Kasai et al., "1/4.mu.m CMOS Isolation Technque Using Selective Epitaxy", IEEE, vol. Ed-34, No. 6, Jun. 1987.

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