Synchronous semiconductor memory device capable of rapidly, high

Details Synchronous semiconductor memory device capable of rapidly, high Synchronous semiconductor memory device capable of rapidly, high

1998-10-13

1999-11-30

Phan, Trong

Static information storage and retrieval

Addressing

Sync/clocking

365194, G11C 800, G11C 700

Patent

active

059954418

ABSTRACT:
An initial delay control data decision circuit detects to which portion of a variable delay circuit a pulse signal of an external clock signal of one cycle is propagated for a predetermined period of time, to determine an initial value for delay control data. Depending on the initial value for delay control data, a delay locked loop circuit configured of the variable delay circuit, a phase comparator circuit, a shift logic circuit, a delay control data holding circuit, a variable constant current circuit and a voltage generating circuit controls phasing of internal and external clock signals.

REFERENCES:
patent: 5247485 (1993-09-01), Ide
patent: 5550783 (1996-08-01), Stephens, Jr. et al.
patent: 5740123 (1998-04-01), Uchida
patent: 5822255 (1998-10-01), Uchida
patent: 5896347 (1999-04-01), Tomita et al.

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