Switching system and method of construction thereof

Multiplex communications – Wide area network – Packet switching

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Details

370 581, 370 60, H04Q 1104

Patent

active

RE0343056

ABSTRACT:
A switching system is disclosed in which a plurality of incoming highways are multiplexed in time division cells that have arrived are written into a buffer memory, the cells thus written are read in an appropriate order, separated in a multiplex way and distributed among a plurality of outgoing highways thereby to perform an exchange operation. An FIFO (First In First Out) buffer stores an empty address of the buffer memory. The address in busy state is controlled in a manner corresponding to the outgoing highways. When a cell is written in the buffer memory, the empty address is taken out of the data output of the FIFO buffer. When the cell is read of the buffer memory the address already read is returned to the data input of the FIFO buffer by an idle address chain.

REFERENCES:
patent: 4603416 (1986-07-01), Servel et al.
patent: 4630258 (1986-12-01), McMillen et al.
patent: 4771419 (1988-09-01), Graves et al.
patent: 4819226 (1989-04-01), Beckner et al.
patent: 4905225 (1990-02-01), Francois et al.

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