Split-polysilicon CMOS process for multi-megabit dynamic memorie

Details Split-polysilicon CMOS process for multi-megabit dynamic memorie Split-polysilicon CMOS process for multi-megabit dynamic memorie

1994-10-13

1996-02-27

Wilczewski, Mary

Fishing, trapping, and vermin destroying

437 60, 437919, H01L 2170, H01L 2700

Patent

active

054948410

ABSTRACT:
This invention is a process for manufacturing dynamic random access memories using stacked container capacitor cells in a split-polysilicon CMOS manufacturing flow. The split-polysilicon flow denotes that N-channel and P-channel transistor gates are formed from a single conductive layer (typically a doped polysilicon layer) using separate masking steps. The focus of this invention is a CMOS manufacturing process flow which permits P-channel source/drain doping subsequent to capacitor formation. A main feature of the process is the deposition and planarization of a thick insulative mold layer subsequent to N-channel device patterning, but prior to P-channel device patterning. In one embodiment of the process, portions of this insulative layer overlying the P-channel transistor regions are removed during the storage-node contact etch. Thus, a low-aspect-ratio etch can be employed to pattern P-channel devices, and a blanket P+ implant may be performed without implanting the P-type impurity into source/drain regions of the N-channel devices. Another important feature of the invention is the incorporation of P-channel gate sidewall spacers and offset P-channel implants into the process flow.

REFERENCES:
patent: 5030585 (1991-07-01), Gonzalez et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5238862 (1993-08-01), Blalock et al.

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