Fishing – trapping – and vermin destroying
Patent
1988-08-02
1990-08-21
Hearn, Brian E.
Fishing, trapping, and vermin destroying
29877, 2281802, 437190, 437192, H01L 2144, H01L 2148
Patent
active
049506234
ABSTRACT:
The invention is a method of forming a solder bump on an under bump metallurgy in which a contact pad on a substrate material is partially covered by a passivation layer upon the substrate material which is non-wettable by solder and in which the under bump metallurgy covers the portions of the contact pad which are not covered by the passivation layer and in which the under bump metallurgy overlaps from the contact pad to cover portions of the passivation layer. The method comprises depositing a layer of solder soluble metal upon the under bump metallurgy so as to cover the under bump metallurgy with the solder soluble metal; coating the deposit of solder soluble metal with a layer of solidified solder while substantially avoiding complete dissolution of the solder soluble metal in the solder; and heating the solder until the layer of solder melts and the deposit of solder soluble metals substantially completely dissolves in the melted solder and the surface tension of the melted solder draws the solder and dissolved solder soluble metal away from the non-wettable passivation layer and into a spheroid solder bump.
REFERENCES:
patent: 3663184 (1972-05-01), Wood et al.
patent: 3839727 (1974-01-01), Herdzik et al.
patent: 4042954 (1977-08-01), Harris
patent: 4237607 (1980-12-01), Ohno
patent: 4273859 (1981-06-01), Mones et al.
patent: 4293637 (1981-10-01), Hatada et al.
patent: 4661375 (1987-04-01), Thomas
P. P. Castrucci, R. H. Collins and R. P. Pecoraro; Terminal Metallurgy System for Semiconductor Devices; IBM Technical Disclosure Bulletin; vol. 9, No. 12, May, 1967.
T. Kawanobe, K. Miyamoto, Y. Inaba; Solder Bump Fabrication by Electrochemical Method for Flip Clip Interconnection; Musashi Works, Hitachi Ltd., 1450 Josuihon-cho, Kodaira-shi, Tokyo, Japan; pp. 149-155.
English Translation; (19) Japan Patent Office (JP); (11) Laid Open Patent Application; (12) Patent Application Publication (B2); S57-11141; (24) (44) Published Mar. 2, 1982.
English Translation; (19) Japan Patent Office (JP); (11) Laid Open Patent Application; (12) Laid Open Patent Publication (A); S59-154041; (43) Laid Open: Sep. 3, 1984.
English Translation; Japanese Patent 60-180146; Collective Forming Method of Solder Bumps; K. Fujiwara, M. Asahi, H. Yoshikiyo and K. Aoki; Applicant: N. Telegrah and K. K. Telephone; Sep. 13, 1985.
Bunch William
Hearn Brian E.
Microelectronics Center of North Carolina
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