Excavating
Patent
1987-01-29
1989-03-07
Atkinson, Charles E.
Excavating
G06F 1110
Patent
active
048113476
ABSTRACT:
A data processing arrangement which comprises a memory device provided with a memory with a first field in which memory words are stored or can be stored and a second field in which an error protection bit can be stored for every memory word from the first field. The memory device further comprises an error protection bit generator for the generation of error protection bits and a coincidence circuit. This coincidence circuit operates in two different modes, on the one hand, an error protection mode in which error protection operations, suh as for example the use of parity bits, take place in the known manner and, on the other hand, a coincidence mode in which the error protection operations are suppressed and replaced by coincidence operations. These coincidence operations make it possible to find out whether access operations are being performed at pre-determined memory addresses. In order to make these coincidnece operations possible, a coincidence bit is stored in the second field at these pre-determined memory addresses before the coincidence circuit is allowed to operate in the coincidence mode.
REFERENCES:
patent: 3427443 (1969-02-01), Apple et al.
patent: 3982111 (1976-09-01), Lerner et al.
patent: 4656631 (1987-04-01), Nowak
patent: 4689772 (1987-08-01), Jordy et al.
Atkinson Charles E.
Barschall Anne E.
Briody Thomas A.
Haken Jack E.
U.S. Philips Corporation
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