Multiplex communications – Wide area network – Packet switching
Patent
1985-07-03
1989-03-07
Chan, Eddie P.
Multiplex communications
Wide area network
Packet switching
364900, G06F 1300
Patent
active
048112771
DESCRIPTION:
BRIEF SUMMARY
The invention relates to communication interfaces and is particularly applicable to communication interfaces for use with computer apparatus and the transmission of messages between computers or computers and other devices connected thereto. The invention is particularly applicable to message transmission between integrated circuit devices.
BACKGROUND TO THE INVENTION
Computer devices and other integrated circuit devices may need to transmit messages to or receive messages from other devices. In some cases the message transmission may occur between two interconnected devices or between a large number of devices forming a network. In such a network one or more of the devices may be in the form of computer apparatus and other devices may comprises a variety of peripheral equipment.
The transmission of data between the integrated circuit devices can be accomplished by a variety of different techniques. For communication over short distances it is common to use a parallel data bus with many signal wires shared between many devices. For communication over longer distances a serial communication system may be preferred with pairs of devices connected by one or two signal wires. The more devices that a shared bus connects, the slower the maximum speed of operation. This imposed a practical limit on the number of devices which may be connected by a shared data bus. Furthermore, it is inconvenient to use many parallel buses in a system on account of the large number of signal lines and difficulties of arranging for communication between devices attached to different buses. There is no limit to the number of devices which may be connected using individual serial connections between pairs of devices provided that each device is equipped with a number of links to which connections can be made. However, existing serial connection systems are too slow, too big or inappropriate in function to be used for general purpose communications between microcomputers and other devices in a system.
OBJECTS OF THE INVENTION
It is an object of the present invention to provide an improved link interface for use in a serial communication system between communicating devices.
It is a further object to provide a link interface which enables two-way communication two devices using non-shared signal wires.
It is a further object of the present invention to provide a communication interface which enables a standard communication procedure to be used by a variety of devices connected into a common network.
It is a further object of the present invention to provide an improved communication interface which will permit communication between a variety of connected devices which do not have a standard wordlength. In this way communication is permitted between devices which do not all use the same number of bits per word in the process carried internally by each device.
It is a further object to provide an improved communication interface for providing serial bit communication which is independent of wordlength.
SUMMARY OF THE INVENTION
The present invention provides a communication interface to enable communication between a device and a microcomputer, or between devices in a network including one or more microcomputers, which interface comprises an output channel for outputting data and an input channel for receiving data.
The interface includes a packet generator coupled to the output terminal. The packet generator outputs bit packets in serial form. Two different formats can be outputted. The first format is a data packet and the second format is an acknowledgement packet. A packet decoder is provided in the interface and is coupled to the input terminal. It receives serial bit packets, of both the data packet and acknowledgement packet type, and determines whether each received packet is a bit packet or an acknowledgement packet. Interlock control circuitry is coupled to the packet generator and to the packet decoder. This control circuitry is responsive to the receipt of a data packet and causes the packet generator to output an ac
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Chesney Henry M.
May Michael D.
Chan Eddie P.
Inmos Limited
Manzo Edward D.
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