Merged CCD/MOS integrated circuit

Details Merged CCD/MOS integrated circuit Merged CCD/MOS integrated circuit

1985-10-17

1989-03-07

Harkcom, Gary V.

Boots, shoes, and leggings

364767, 364841, 364862, G06F 752, G06F 716, G06F 700

Patent

active

048112704

ABSTRACT:
A digital integrated circuit that includes on a common substrate both charge-coupled device (CCD) circuitry and metal-oxide semiconductor (MOS) circuitry that combine together efficiently to implement a complex digital function such as a multi-bit multiplier or divider. The CCD circuitry includes an array of full adder cells and the MOS circuitry selectively processes and channels certain bits of a plurality of digital input bits to the individual full adder cells, such processing being based on other of the digital input bits. The introduction of MOS logic into the CCD circuit permits greater flexibility in the layout and interconnection of the individual full adder cells and permits the utilization of more efficient algorithms than otherwise could be used in circuits having CCD elements alone.

REFERENCES:
patent: 4032767 (1977-06-01), Lagrado
patent: 4446532 (1984-05-01), Baertsch et al.
patent: 4464728 (1984-08-01), Nash
patent: 4523290 (1985-06-01), Hyatt
patent: 4625293 (1986-11-01), Vogelsing et al.
patent: 4638449 (1987-01-01), Frey
patent: 4646257 (1987-02-01), Essig et al.
patent: 4665500 (1987-05-01), Poland
W. Bucklen et al., "Single-chip Digital Multipliers Form Basic DSP Building Blocks," Electron Device News, Apr. 1, 1981, pp. 153-163.
T. A. Zimmerman et al., "Digital Charge-Coupled Logic (DCCL)," IEEE J. Solid State Circuits, Oct. 1977, pp. 473-485.
J. G. Nash, "An 8-Bit Parallel CCD Digital Multiplier," Proceedings of IEEE Custom Integrated Circuits Conference, Rochester, N.Y., May 17-19, 1982.
Dawson et al, "A CMOS/Buried-n-channel CCD Compatible Process for Analog Signal Processing Applications", RCA Review, vol. #38, #3, pp. 406-435, Sep. 1977.

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