Method of making trench-incorporated monolithic semiconductor ca

Details Method of making trench-incorporated monolithic semiconductor ca Method of making trench-incorporated monolithic semiconductor ca

1985-10-30

1987-11-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 67, 437 31, 437249, 437919, H01L 21302, H01L 2176, H01L 2170

Patent

active

047043687

ABSTRACT:
A high density integrated circuit structure, for example a dynamic memory cell, is described which includes an active/passive device in combination with a capacitor structure. The capacitor structure is of the polysilicon-oxide-silicon type and is formed on the sidewalls of a mesa-shaped and dielectrically isolated region of silicon material resulting from the formation of an isolation trench in the silicon. The trench is filled with a plastic material, such as polyimide. The capacitor is formed by the isolated region of silicon material which functions as the first capacitor plate, a doped polysilicon layer provided on the vertical walls of the mesa serving as the second capacitor plate and a thin dielectric layer interposed between the two plates serving as the capacitor's dielectric. Since the polysilicon is wrapped around the periphery of the mesa as a coating on the vertical sidewalls thereof, it gives rise to a large storage capacitance without an increase in the cell size.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 3876992 (1975-04-01), Pricer
patent: 4017885 (1977-04-01), Kendall et al.
patent: 4225945 (1980-09-01), Kuo
patent: 4327476 (1982-05-01), Iwai et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4381953 (1983-05-01), Ho et al.
patent: 4534826 (1985-08-01), Goth et al.
patent: 4577395 (1986-03-01), Shibata
patent: 4645564 (1987-02-01), Morie et al.
C. G. Jambotkar, "Very Dense One-Device Fet Memory Cell", IBM Technical Disclosure Bulletin, vol. 25, No. 2, Jul. 1982, pp. 593-596.

Affiliated with

Also associated with

Rating

Method of making trench-incorporated monolithic semiconductor ca does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of making trench-incorporated monolithic semiconductor ca, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making trench-incorporated monolithic semiconductor ca will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1674332