Protection circuit for a semiconductor integrated circuit having

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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Details

361 58, 361 91, 361111, 357 2313, 357 42, H01L 2702

Patent

active

048111554

ABSTRACT:
Two resistors are connected in series between an input bonding electrode and an internal circuit, and respective conducting terminals of a first bipolar transistor are connected between the two resistors and a GND bonding electrode which is connected to the internal circuit. Respective conducting terminals of a second bipolar transistor are connected between the two resistors and a V.sub.DD bonding electrode which is connected to the internal circuit. Control terminals of the respective ones of the first and second bipolar transistors are connected to the GND bonding electrode respectively.

REFERENCES:
patent: 4476476 (1984-10-01), Yaet et al.
patent: 4617482 (1986-10-01), Matsuda

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