Multiprocessor cache coherency tester that exercises the coheren

Details Multiprocessor cache coherency tester that exercises the coheren Multiprocessor cache coherency tester that exercises the coheren

1992-08-14

1994-10-11

Beausoliel, Jr., Robert W.

395425, G06F 1100

Patent

active

053554710

ABSTRACT:
A cache coherency test exercises cache coherency logic exhaustively such that any cache coherency failures liable to occur will occur. The CPU(s) which caused the failure is automatically identified by performing an automatic CPU sort. In particular, cache coherency is tested by causing each processor in the system to perform a sequence of read and write accesses to main memory and to its own cache memory so as to cause substantially every possible sequence of cache coherency bus operations. Each processor tests consistency of data read by it with data written by it. As long as no processor detects an error, read and write accesses are continued for a predetermined period of time. When any processor detects an error, each CPU is disabled, one at a time, to see if the remaining CPUs can run the test successfully. If they do not, then every combination of two CPUs are disabled, then every combination of three, etc. In this manner, a maximum running set of CPUs is identified. CPU failures are verified by substituting, one at a time, failing CPUs for a passing CPU and again running the test. If the test is unsuccessful, then failure of the CPU is presumed to be conclusive.

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