Circuit configuration for transforming the logical address space

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395375, 395725, 3642443, 364247, 3642545, 3642551, 3642563, 364DIG1, G06F 1210, G06F 932

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053554639

ABSTRACT:
A circuit configuration for adapting a logical address space of a processor unit to a physical address space of a memory includes, an interpretation unit, and data and control lines connecting the interpretation unit to the processor unit. The interpretation unit includes a register having a first register region and having a second register region to be written into by the processor unit. The interpretation unit continuously evaluates a logic state of the processor unit, writes contents of the second register region into the first register region at defined logic states and outputs contents of the first register region as an address. A linking unit is connected by address lines to the processor unit, to the interpretation unit and to the memory. The linking unit forms a total address for the memory from addresses transferred by the interpretation unit and the processor unit.

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