Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1992-02-11
1994-10-11
LaRoche, Eugene R.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36523001, 36523002, G11C 700
Patent
active
053553489
ABSTRACT:
The disclosed is an DRAM which is accessible in response to four-state address signal. A two-state address signal generator receives the four-state address signal respectively defined by four voltage levels and converts it to a row address signal and a column address signal which are two-state address signals. Converted address signals are supplied to a row decoder and a column decoder, respectively. Address signals for access are supplied without adopting an address multiplexing system, so that it is possible to perform accurate addressing under the requirement of high speed operation. In addition, the number of sense amplifiers to be activated in one read operation can be reduced, and therefore power consumption can be also reduced.
REFERENCES:
patent: 3972031 (1976-07-01), Riemenschneider
patent: 4581722 (1986-04-01), Takemae
patent: 4636990 (1987-01-01), Buscaglia et al.
patent: 4845678 (1989-07-01), van Berkel
patent: 4929945 (1990-05-01), Kushiyama
patent: 5105386 (1992-04-01), Andoh et al.
patent: 5161218 (1992-11-01), Catlin
IBM Technical Disclosure Bulletin vol. 29 No. 9 Feb. 1987.
LaRoche Eugene R.
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Tan
LandOfFree
Semiconductor memory device and memory access system using a fou does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and memory access system using a fou, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and memory access system using a fou will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1664372