Word line selection circuit for simultaneously selecting a plura

Details Word line selection circuit for simultaneously selecting a plura Word line selection circuit for simultaneously selecting a plura

1993-07-01

1994-10-11

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 36518901, 307449, 307463, G11C 800

Patent

active

053553462

ABSTRACT:
A selection circuit of the present invention comprises a plurality of word lines each of which is coupled to a plurality of memory cells, the word lines including first and second groups of word lines, a first decode line group having a plurality of first decode lines each of which is coupled to the first group of the word lines, a second decode line group having a plurality of second decode lines each of which is coupled to the second group of the word lines, a plurality of address input terminals applied to an address signal, a first input terminal applied to a first signal, a second input terminal applied to a second signal, a first selecting switch coupled to the first and second decode line groups and the address input terminals for selecting one of the decode lines in response to the address signal, a second selecting switch coupled to the first decode line group and the first input terminal for selecting the first decode lines in response to the first signal and a third selecting switch coupled to the second decode line group and the second input terminal for selecting the second decode lines in response to the second signal.

REFERENCES:
patent: 4584674 (1986-04-01), Watanabe
patent: 4596000 (1986-06-01), Wiedmann
patent: 4845678 (1989-07-01), Van Berkel et al.
patent: 4868788 (1989-09-01), Jinbo
patent: 4954994 (1990-09-01), Hashimoto
patent: 5282175 (1994-01-01), Fujita et al.
patent: 5289429 (1994-02-01), Watanabe
patent: 5293340 (1994-03-01), Fujita
patent: 5297105 (1994-03-01), Matsui et al.

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