Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead
Patent
1994-03-11
1996-07-30
Hille, Rolf
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With contact or lead
257692, 257773, 257774, 439 65, 439 68, 439278, 439692, H01L 23049, H01L 23055, H01L 23498, H01L 2348
Patent
active
055414494
ABSTRACT:
A semiconductor die carrier may include an insulative substrate; an array of groups of multiple electrically conductive contacts arranged in rows and columns on the insulative substrate, wherein the groups from adjacent rows are staggered as are the groups from adjacent columns, and a portion of each group overlaps into an adjacent row or an adjacent column of the groups of the array; a semiconductor die; and structure for providing electrical connection between the semiconductor die and the conductive contacts. A semiconductor die carrier may also include an insulative substrate; a plurality of leads each having an external portion extending out of the semiconductor die carrier from a lower surface of the insulative substrate and an internal portion located within the semiconductor die carrier at an upper surface of the insulative substrate; a semiconductor die; and a layer of conductive material in contact with conductive portions of the semiconductor die and also in contact with the internal portions of the leads.
REFERENCES:
patent: 3337838 (1967-08-01), Damiano et al.
patent: 3366915 (1968-01-01), Miller
patent: 3444506 (1969-05-01), Wedekind
patent: 3848221 (1974-11-01), Lee, Jr.
patent: 4572604 (1986-02-01), Ammon et al.
patent: 4616406 (1986-10-01), Brown
patent: 4654472 (1987-03-01), Goldfarb
patent: 4655526 (1987-04-01), Shaffer
patent: 4698663 (1987-10-01), Sugimoto et al.
patent: 4734042 (1988-03-01), Martens et al.
patent: 4897055 (1990-01-01), Jurista et al.
patent: 4943846 (1990-07-01), Shirling
patent: 4959750 (1990-09-01), Cnyrim et al.
patent: 4975066 (1990-12-01), Sucheski et al.
patent: 4997376 (1991-03-01), Buck et al.
patent: 5015207 (1991-05-01), Koepke
patent: 5037311 (1991-08-01), Frankeny et al.
patent: 5071363 (1991-12-01), Reylek et al.
patent: 5081563 (1992-01-01), Feng et al.
patent: 5117069 (1992-05-01), Higgins, III
patent: 5123164 (1992-06-01), Shaheen et al.
patent: 5137456 (1992-08-01), Desai et al.
patent: 5281151 (1994-01-01), Arima et al.
patent: 5309024 (1994-05-01), Hirano
patent: 5326936 (1994-07-01), Taniuchi et al.
patent: 5330372 (1994-07-01), Pope et al.
patent: 5334279 (1994-08-01), Gregoire
patent: 5342999 (1994-08-01), Frei et al.
patent: 5351393 (1994-10-01), Gregoire
patent: 5371404 (1994-12-01), Juskey et al.
patent: 5376825 (1994-12-01), Tukamoto et al.
patent: 5390412 (1995-02-01), Gregoire
AMP Product Guide, Printed Circuited Board Connectors 3, pp. 3008, 3067-3068, 3102-3103, 3122-3123.
George D. Gregoire, "3-Dimensional Circuitry Solves Fine Pitch SMT Device Assembly Problem," Connection Technology.
Dimensional Circuits Corporation, "Dimensional Circuits Corp. Awarded Two U.S. Patents." D.C.C. News, Apr. 5, 1994.
George D. Gregoire, "Very Fine Line Recessed Circuitry--A New PCB Fabrication Process".
R. R. Tummala et al., "Microelectronics Packaging Handbook," Van Nostrand Reinhold, 1989, pp. 38-43, 398-403, 779-791, 853-859, and 900-905.
"Packaging," Intel Corporation, 1993, pp. 2-36, 2-96, 2-96, 2-100, 3-2, 3-24, and 3-25.
Crane, Jr. Stanford W.
Portuondo Maria M.
Hardy David B.
Hille Rolf
The Panda Project
LandOfFree
Semiconductor chip carrier affording a high-density external int does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor chip carrier affording a high-density external int, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip carrier affording a high-density external int will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1661326