Patent
1995-11-30
1998-07-21
Bowler, Alyssa H.
39518204, 39518206, G06F 1100
Patent
active
057845379
ABSTRACT:
An instruction for returning to a ROM is written to a position where data is not broken even if a next correction is executed in order not to the content of a register even if an interruption processing for correction and a processing for returning a ROM program are executed. A microcomputer connected through a serial i/O bus, an EEROM, and a correction data writing device comprises a CPU, a RAM, a ROM, a PC comparison register section, a ROM correction processing circuit having a PC value latch section, and a serial i/O section. The CPU sequentially executes an internal sequence control of the microcomputer and a logical operation in accordance with instructions written in the ROM as a program in advance. The RAM temporarily saves intermediate processing data of, e.g. calculation, or saves an adjustment value transferred from the EEPROM when the program is actually executed.
REFERENCES:
patent: 5454100 (1995-09-01), Sagane
patent: 5574926 (1996-11-01), Miyazawa et al.
patent: 5592613 (1997-01-01), Miyazawa et al.
patent: 5619678 (1997-04-01), Yamamoto et al.
Miyazawa Azuma
Mizobuchi Koji
Suzuki Takashi
Bowler Alyssa H.
Davis Jr. Walter D.
Olympus Optical Co,. Ltd.
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