Multiplex communications – Pathfinding or routing – Switching a message which includes an address header
Patent
1995-12-29
1998-07-21
Olms, Douglas W.
Multiplex communications
Pathfinding or routing
Switching a message which includes an address header
370467, H04L 2910
Patent
active
057843708
ABSTRACT:
An extender circuit provides a serial communication interface between an ATM layer and a PHY layer. The extender circuit includes a first circuit serially coupled to a second circuit. The first circuit is coupled to the ATM layer and communicates in parallel with the ATM layer. The first circuit is operable to receive a control signal from the ATM layer. The second circuit is coupled to the PHY layer and communicates in parallel with the PHY layer. The first circuit does not transmit the control signal to the second circuit. The second circuit regenerates the control signal at the PHY layer. The first circuit and the second circuit function in like manners. The first circuit receives a control signal generated by the ATM layer. The control signal may comprise a start of cell signal. The first circuit transmits a first sequence of signals to the second circuit. The second circuit detects the occurrence of the first sequence of signals and reproduces the control signal at the PHY layer when the first sequence of signals is not detected. The first sequence of signals may comprise an idle character. In another embodiment, the first circuit transmits a second sequence of signals to the second circuit. The second circuit reproduces the control signal at the PHY layer when the second circuit detects the first sequence of signals followed by the second sequence of signals.
REFERENCES:
patent: 5134702 (1992-07-01), Charych et al.
patent: 5412783 (1995-05-01), Skokan
patent: 5418786 (1995-05-01), Loyer
patent: 5485456 (1996-01-01), Shtayer et al.
patent: 5568470 (1996-10-01), Ben-Nun
patent: 5610921 (1997-03-01), Christensen
Des Young, et al., "UTOPIA, An ATM-PHY Interface Specification", The ATM Forum, pp. 1-19, Level 1, Ver. 2.01, (Mar. 1994).
Cypress Semiconductor Data Book Memories DataCom FCT Logic PC Products, Hotlink Data Sheet (CY7B923,CY7B933), Doc. No. 38-00189-F, pp. 7:8-34 (1995).
Cypress Semiconductor Data Book Memories DataCom FCT Logic PC Products, 512.times.9 Cascadable Clocked and 2K .times. 9 Cascadable Clocked Data Sheet (CY7C451,CY7C453), Doc. 38-00125-E, pp. 5:115-137 (1995).
Cypress Semiconductor Programmable Logic Databook, 32-Macrocell Flash CPLD (CY7C371), pp. 3:99-106 (1994/1995).
J. Bellamy, Digital Telephony, John Wiley & Sons, Inc., Second Ed., p. 22.
Craig Rich, et al., Cypress Semiconductor Design SuperCon '95, Digital Communications Design Conference, "Extending the UTOPIA Interface in ATM Applications", (1995).
DAVIC Specification, "Description of DAVIC Functionalities", Part 1,2,3,4,6,7,8,9, (Jun. 1995).
Cypress Semiconductor Corp.
Olms Douglas W.
Phillips Matthew C.
LandOfFree
Method and apparatus for regenerating a control signal at an asy does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for regenerating a control signal at an asy, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for regenerating a control signal at an asy will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1654087