Vertical floating-gate transistor

Details Vertical floating-gate transistor Vertical floating-gate transistor

1989-12-08

1991-05-14

Larkins, William D.

357 234, H01L 27115, H01L 29788

Patent

active

050160680

ABSTRACT:
An electrically erasable, progammable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

REFERENCES:
patent: 3518509 (1970-06-01), Cullis
patent: 4222062 (1980-09-01), Trotter
patent: 4334235 (1982-06-01), Nishizawa
Ammar et al., IEEE Transactions on Electron Devices, vol. ED27, No. 5, May 1980, pp. 907-914.
Rodgers et al., IEEE Journal of Solid State Circuits, vol. SC12, No. 5, Oct. 1977, pp. 515-524.
IBM Tech. Discl. Bul., vol. 14, No. 3, Aug. 1971, p. 751, "High Speed Epitaxial Field-Effect Devices", Magdo et al.

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