1989-12-08
1991-05-14
Larkins, William D.
H01L 2978
Patent
active
050160672
ABSTRACT:
A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode. Series drain resistance, and gate-to-drain capacitance, is minimized by a deeper implant of the drain region away from the trench and under the electrical interconnection to the drain diffusion.
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Ammar et al, IEEE Transactions on Electron Devices, vol. ED27, No. 5, May 1980, pp. 907-914.
Rodgers et al., IEEE Journal of Solid State Circuits, vol. SC12, No. 5, Oct. 1977, pp. 515-524.
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IBM Tech. Discl. Bul., vol. 14, No. 3, Aug. 1971, p. 751, "High-Speed Epitaxial Field Effect Devices", Magdo et al.
Demond Thomas W.
Larkins William D.
Lindgren Theodore D.
Sharp Melvin
Texas Instruments Incorporated
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