Clock recovery phase lock loop having digitally range limited op

Details Clock recovery phase lock loop having digitally range limited op Clock recovery phase lock loop having digitally range limited op

1990-02-15

1991-05-14

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Plural a.f.s. for a single oscillator

307516, 307526, 328134, 331 1A, 331 17, 331 27, H03L 7087, H03L 7089

Patent

active

050159704

ABSTRACT:
A PLL architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single VCO. The coarse adjustment feedback loop includes two digital counters set to divide the VCO output frequency by two different numbers. The outputs of the counters are coupled to the inputs of respective phase-frequency detectors, and the pump-up output of one of the detectors and the pump-down output of the other detector are used as the coarse adjustment pump-up and pump-down signals, respectively, in the coarse adjustment feedback loop. The coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop.

REFERENCES:
patent: 3610954 (1971-10-01), Treadway
patent: 4339731 (1982-07-01), Adams
patent: 4565976 (1986-01-01), Campbell
patent: 4686481 (1987-08-01), Adams
Llewellyn et al, "A 33 Mb/s Data Synchronizing Phase-Locked-Loop Circuit", 1988 IEEE International Solid-State Circuits Conference, Feb. 17, 1988, pp. 12-13, 276, 277.

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